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dual 12-bit, high bandwidth, multiplying dac with 4-quadrant resistors and parallel interface AD5405 rev. 0 in fo rmation furn is h e d by an al o g dev i ces is believed to be a ccu rate and r e liable. how e ver, no r e spons i bili ty is assumed by analog devices fo r its use, nor f o r an y i n fri n geme nt s of p a t e nt s or ot her ri g h t s o f th ird parties th at may result fro m its use . specifications subject to chan g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot he rwi s e un der a n y p a t e nt or p a t e nt r i ghts of anal og de vices. trad emarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features on chip 4-quadrant resistors a llow flexible output ranges 10 mhz multiplying bandwidt h fast paralle l in terface write cycle: 58 msps 2.5 v to 5.5 v s u pply operation 10 v refer e nce input extended t e mperature r a nge: ? 40 c to 12 5c 40-lea d lfcsp package guarantee d m o notonic 4-qua d rant m u ltiplication power-on reset readback func tion .5 a ty pical current consu m ption applic ati o ns portable batter y -powered applications waveform gen e rators analog processing instrumentation applications programmable amplifiers and attenuators digitall y-controlled calibratio n programmable filters and osci llators composite video ultrasound gain, offset, an d voltage trim ming general description the AD5405 1 i s a d u a l c m o s , 1 2 - b i t , c u r r e n t o u t p u t d i g i t a l - t o -a nalog co n v er t e r (d a c ).this de vice op era t es f r o m a 2.5 v t o 5 . 5 v p o we r supply , ma k i ng it s u i t e d to b a tte r y - p owe r e d a nd o t h e r a p plic a t ion s . the a p plie d exter n al r e fer e n c e i n p u t v o l t a g e ( v ref ) det e r m in es t h e f u l l -s cale o u t p u t c u r r en t. a n in teg r a t e d fe e d b a ck r e sis t o r (r fb ) p r o v ides tem p er a t ur e t r ackin g and f u l l -s c a le v o l t a g e o u t p u t w h en com b in e d wi t h a n ext e r n al i-t o -v p r ecisio n a m plif ier . this de vice a l s o con t a i n s a l l t h e 4- q u adra n t r e sist o r s n e ce ss a r y fo r b i p o la r o p er a t io n a nd o t h e r co nf i g ur a t io n m o de s . this d a c u t i l i z es da t a r e ad b a ck, al lo win g t h e us er t o r e ad t h e co n t e n ts o f t h e d a c r e g i s t er v i a t h e d b p i n s . on p o w e r - up , t h e in t e r n al r e g i st er a nd l a t c h e s a r e f i l l e d wi th zer o s a nd t h e d a c output s are at z e ro s c a l e. a s a re su lt of man u f a c t u r e w i t h a c m o s su b m i c ron p r o c e s s , t h e de vice o f fers exce l l en t 4 - q u adr a n t m u l t i p li ca t i o n cha r ac t e r i s t i c s, wi t h la rg e sig n a l m u l t i p l y in g ban d wid t h s o f u p t o 10 mh z. the AD5405 has a 6 mm 6 mm, 40-lead lfcs p p a c k a g e . 1 us patent number 5,689,257. v ref a AD5405 v ref b v dd db0 db11 data inputs dac a/b cs r/w gnd control logic input buffer latch i out 1b i out 1a 12-bit r-2r dac a r fb a power-on reset 12-bit r-2r dac b latch r1 2r r1a r2 2r r3 2r r3a r2a r2_3a r2 2r r3 2r r3b r2b r2_3b rfb 2r r1 2r rfb 2r r1b i out 2a i out 2b ldac 04463-0-001 r fb b f i g u re 1. a d 54 05 f u nc t i o n a l b l o c k d i ag r a m
AD5405 rev. 0 | page 2 of 24 table of contents specifications ..................................................................................... 3 timing characteristics ..................................................................... 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 te r m i no l o g y .................................................................................... 13 general description ....................................................................... 14 dac section ................................................................................ 14 circuit operation ....................................................................... 14 single-supply applications ........................................................ 15 positive output voltage ............................................................. 15 adding gain ................................................................................ 15 used as a divider or programmable gain element ............... 16 reference selection .................................................................... 16 amplifier selection .................................................................... 16 parallel interface ......................................................................... 17 microprocessor interfacing ....................................................... 17 pcb layout and power supply decoupling ........................... 17 evaluation board for the dacs ................................................ 18 overview of ad54xx devices ....................................................... 22 outline dimensions ....................................................................... 23 ordering guide .......................................................................... 23 revision history 7/04revision 0: initial version
AD5405 rev. 0 | page 3 of 24 specifications 1 v dd = 2.5 v to 5.5 v, v ref a = v ref b = 10 v, i out 2 = 0 v. all specifications t min to t max, unless otherwise noted. dc performance measured with op1177, ac performance with ad9631, unless otherwise noted. table 1. parameter min typ max unit conditions static performance resolution 12 bits relative accuracy 1 lsb differential nonlinearity ?1/+2 lsb guaranteed monotonic gain error 25 mv gain error temp coefficient 2 5 ppm fsr/c bipolar zero-code error 25 mv output leakage current 1 na data = 0x0000, t a = 25c, i out 1 10 na data = 0x0000 h , i out 1 reference input 2 typical resistor tc = ? 50 ppm/c reference input range 10 v v ref a, v ref b input resistance 8 10 12 k? dac input resistance v ref a to v ref b input resistance mismatch 1.6 2.5 % typ = 25c, max = 125c r 1 , r fb resistance 16 20 24 k? r 2 , r 3 resistance 16 20 24 k? r 2 to r 3 resistance mismatch .06 .18 % typ = 25c, max = 125c digital inputs/output 2 input high voltage, v ih 1.7 v v dd = 2.5 v to 5.5 v input low voltage, v il 0.8 v v dd = 2.7 v to 5.5 v 0.7 v v dd = 2.5 v to 2.7 v input leakage current, i il 1 a input capacitance 10 pf v dd = 4.5 v to 5.5 v output low voltage, v ol 0.4 v i sink = 200 a output high voltage, v oh v dd ? 1 v i source = 200 a v dd = 2.5 v to 3.6 v output low voltage, v ol 0.4 v i sink = 200 a output high voltage, v oh v dd ?0.5 v i source = 200 a dynamic performance 2 reference multiplying bw 10 mhz v ref = 5 v pk-pk, dac loaded all 1s output voltage settling time 80 120 ns measured to 1 mv of fs. r load = 100 ?, c load =15 pf. dac latch alternately loaded with 0s and 1s. digital delay 20 40 ns digital-to-analog glitch impulse 3 nv-s 1 lsb change around major carry, v ref = 0 v multiplying feedthrough error ?75 db dac latch loaded with all 0s. reference = 10 khz output capacitance 2 pf dac latches loaded with all 0s 4 pf dac latches loaded with all 1s digital feedthrough 5 nv-s feedthrough to dac output with cs high and alternate loading of all 0s and all 1s total harmonic distortion ?75 db v ref = 5 v p-p, all 1s loaded, f = 1 khz ?75 db v ref = 5 v, sine wave generated from digital code output noise spectral density 25 nv/hz @ 1 khz
AD5405 rev. 0 | page 4 of 24 parameter min typ max unit conditions sfdr performance (wideband) clock = 10 mhz 500 khz f out 55 db 100 khz f out 63 db 50 khz f out 65 db clock = 25 mhz 500 khz f out 50 db 100 khz f out 60 db 50 khz f out 62 db sfdr performance (narrow band) clock = 10 mhz 500 khz f out 73 db 100 khz f out 80 db 50k hz f out 87 db clock = 25 mhz 500 khz f out 70 db 100 khz f out 75 db 50k hz f out 80 db intermodulation distortion clock = 10 mhz f 1 = 400 khz, f 2 = 500 khz 65 db f 1 = 40 khz, f 2 = 50 khz 72 db clock = 25 mhz f 1 = 400 khz, f 2 = 500 khz 51 db f 1 = 40 khz, f 2 = 50 khz 65 db power requirements power supply range 2.5 5.5 v i dd 10 a logic inputs = 0 v or v dd power supply sensitivity 2 0.001 %/% ?v dd = 5% 1 temperature range for y version is ?40c to +125c. 2 guaranteed by design, not subject to production test.
AD5405 rev. 0 | page 5 of 2 4 timing characteristics v dd = 2.5 v t o 5.5 v , v ref = 5 v , i ou t 2 = 0 v . a l l sp e c if ic a t io n s t mi n to t max, u n l e ss ot he r w i s e not e d. table 2. parameter 1 , 2 limit at t min , t ma x u n i t c o n d i t i o n s / c o m m e n t s write mode t 1 0 n s m i n r/ w to cs setup tim e t 2 0 n s m i n r/ w to cs hold time t 3 1 0 n s m i n cs low time t 4 10 ns min ad d r ess setup time t 5 0 ns min address hold time t 6 6 ns min data setup time t 7 0 ns min data hold time t 8 5 n s m i n r/ w high to cs low t 9 7 n s m i n cs min high time data readback mode t 10 0 ns typ address setup ti me t 11 0 ns typ ad d r ess hold time t 12 5 ns typ data access time 3 5 n s m a x t 13 5 ns typ bus relin q uish time 1 0 n s m a x 1 s e e temp erature range for y versio n is ?40c to +125c. guara nteed by design and ch aracte rization, not subject to pr od uctio n te s t . f i g u r e 2. 2 a l l i n put si gn a ls a r e sp eci f i e d wi t h t r = t f = 5n s (10% t o 9 0 % of vd d ) a n d t i m e d from a vo lt a g e l e vel o f (v il + v ih ) / 2. digital output timi ng meas ured with load circuit in . f i g u r e 3 t 7 data valid t 6 t 2 cs r/w data t 1 data valid t 2 t 13 t 12 t 3 t 8 t 9 daca/dacb t 4 t 5 t 11 t 10 04463-0-002 f i g u re 2. ti ming d i ag r a m i ol 200 a i oh 200 a c l 50pf to output pin v oh (min) + v ol (max) 2 04463-0-003 f i gure 3 . l o a d cir c ui t fo r d a ta t i mi ng sp eci f i c a t io ns
AD5405 rev. 0 | page 6 of 2 4 absolute maximum ratings t a = 2 5 c , u n l e ss ot he r w i s e not e d. table 3. p a r a m e t e r r a t i n g v dd to gnd ? 0.3 v to +7 v v ref a, v ref b, r fb a, r fb b to gnd ? 12 v to +12 v i ou t 1, i ou t 2 to gn d ? 0.3 v to +7 v logic inputs and output 1 ? 0.3v to v dd + 0.3 v operating tem p erature range automotive (y v e rsion) ? 40c to +125c storage temperature range ? 65c to +150c junction tempe r ature 150c 40-lead lfcsp, ja thermal imp e dance 30c/w lead temperature, soldering (10 sec.) 300c ir reflow, peak temperature (< 20 sec.) 235c 1 over v o lt a g es a t d b x, ldac , cs , and w /r a r e cla m ped by i n t e rn a l di ode s . current should be limited to the maximum ratings given. s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s ra t i n g onl y ; f u n c t i o n al o p era t ion o f t h e de vice a t t h es e o r an y o t h e r con d i t io ns a b o v e t h o s e i ndic a te d i n t h e op er a t io na l s e c t io n s o f t h is sp e c if ic a t ion is n o t i m plie d . e x p o sur e t o ab s o lute m a x i m u m r a t i ng c o nd it i o ns for e x te nd e d p e r i o d s m a y af fe c t d e v i c e rel i a b i l it y . esd caution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
AD5405 rev. 0 | page 7 of 2 4 pin conf iguration and fu nction descriptions pin 1 indica t o r AD5405 top view 1 r1a 2 r2a 3 r2_3a 4 r3a 5 v ref a 6 dgnd 7 ldac 8 dac a/b 9 nc 10 db11 nc = n o c o n ne c t d b 10 11 db9 1 2 db8 1 3 db7 1 4 db6 1 5 db5 1 6 db4 1 7 db3 1 8 db2 1 9 db1 2 0 30 r1b 29 r2b 28 r2_3b 27 r3b 26 v re f b 25 v dd 24 clr 23 r/w 22 cs 21 db0 40 r fb a 39 i out 2 a 38 i out 1a 37 n c 36 n c 35 n c 34 n c 33 i out 1 b 32 i out 2 b 31 r fb b 04463-0-004 f i gure 4. pin config ur ation ta ble 4. pi n f u nct i on d e s c ri pt i o ns pin no. mnemonic function 1 to 4 r1a to r3 a dac a 4-quad ra nt resistors. all o w a number of c o nf iguration modes, including bipola r operati on with minimum of external compon e n ts. 5, 26 v ref a, v ref b dac reference voltage input terminal s. 6 dgnd digital ground pin. 7 ldac load dac input. allows as ynchr o nous or sync hr onous updates to the dac outp ut. the dac is asynchronously updated when this signal go es low. alternative l y, if this line is held permanent l y low, an automatic or synchron ous up d a te mod e is sel e cted whereby the dac is updat e d on the rising edge of cs . 8 d a c a/b selects dac a or b. low sele cts dac a, while hi gh selects dac b. 9, 34, 35, 36, 37 nc not internally connected. 10 to 21 db11 to db0 paralle l data bit s 11 through 0. 22 cs chip select inpu t. active low. us ed in conjunctio n with r/ w to loa d paralle l d a ta to the input latch or to read data from the d a c register. edg e sensitive; when pulled high, the dac data is latched. 23 r/ w read/ w rite. when low, used in conj unction wit h cs to load paral l e l d a ta. when hi gh, used in conjunction with cs to read back contents of dac register. 24 clr active low control input. clears dac output and input and dac registers. 2 5 v dd positive power s u pply input. t h ese parts ca n be operated from a supply of 2.5 v to 5.5 v. 26 to 30 r3b to r1b dac b 4-quad rant resistors. all o w a number of c o nf iguration modes, including bipola r operati on with a minimum of external compon e n ts. 3 2 i ou t 2b dac a analog ground. t h is pin typically sh ould be tied to the a n alog ground of the system, but may be biased to achieve si ngle-supply op erati o n. 3 3 i ou t 1b dac b current outputs. 3 8 i ou t 1a dac a current outputs. 3 9 i ou t 2a dac a analog ground. t h is pin typically sh ould be tied to the a n alog ground of the system, but may be biased to achieve si ngle-supply op erati o n. 31, 40 r fb b, r fb a ex ternal amplifier output.
AD5405 rev. 0 | page 8 of 2 4 typical perf orm ance cha r acte ristics ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 inl ( l sb) 2000 1 500 500 1000 0 2500 300 0 3 5 0 0 4000 code 04463-0-030 t a = 25c v ref = 10v v dd = 5v f i g u re 5. inl v s . co de (1 2-bit da c ) ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 dnl (ls b ) 2000 1 500 500 1000 0 2500 300 0 3 5 0 0 4000 code 04463-0-031 t a = 25c v ref = 10v v dd = 5v f i g u re 6. dnl v s . code ( 12-b i t da c ) ? 0.3 ? 0.2 ? 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 inl ( l sb) 6 5 34 2 789 1 0 reference voltage 04463-0-032 max inl min inl t a = 25c v ref = 10v v dd = 5v f i gure 7. inl v s . r e f e r e nc e v o lt age ?0.70 ?0.65 ?0.60 ?0.55 ?0.50 ?0.45 ?0.40 dnl (ls b ) 6 5 34 27 8 9 reference voltage 04463-0-034 1 0 min dnl t a = 25c v ref = 10v v dd = 5v f i gure 8. dnl v s . r e fer e n c e v o ltag e ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 e rror (mv ) ?60 ? 40 ?20 0 20 40 60 80 100 120 140 temperature ( c) 04463-0-034 v dd = 5v v dd = 2.5v v ref = 10v f i gure 9. g a in e rror v s . t e mper atur e input voltage (v) curre nt (ma) 8 5 0 5.0 7 6 3 1 4 2 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 t a = 2 5 c v dd = 5v v dd = 3v v dd = 2.5v 04463-0-013 f i gure 10. sup p l y current v s . l o gic i n p u t v o ltag e
AD5405 rev. 0 | page 9 of 2 4 0 0.2 0.4 0.6 0.8 1.0 i out le akage (na) 1.2 1.4 1.6 40 20 ?2 0 0 ?40 60 80 1 0 0 1 2 0 temperature (c) 04463-0-036 i out 1 v dd 5v i out 1 v dd 3v f i g u re 11. i ou t 1 l e a k ag e cu rrent v s . t e mpe r at u r e 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 curre nt ( a) ?60 ? 40 ?20 0 20 40 60 80 100 120 140 temperature ( c) 04463-0-037 t a = 25c v dd = 5v v dd = 2.5v all 0s all 1s all 0s all 1s f i gure 12. sup p l y current v s . t e mper at ur e 0 2 4 6 8 10 12 14 i dd (ma) 10 k 1k 1 0 100 1 100k 1m 1 0 m 1 0 0 m frequency (hz) 04463-0-038 t a = 25c loading zs to fs v dd = 5v v dd = 3v v dd = 2.5v f i gure 13. sup p l y current v s . u p date r a te ? 102 ?66 ?54 ?42 ?30 ?18 ?6 6 1 100 1k 10k 100k 1m 10m 100m frequency (hz) gain ( d b) t a = 25 c loading zs to fs 0 ?60 ?48 ?36 ?24 ?12 ?84 ?72 ?78 ?90 ?96 t a = 25 c v dd = 5v v ref = 3.5v input c comp =1 . 8 p f ad8038 amplifier AD5405 dac all on db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 all off 04463-0-014 10 f i gure 14. reference mult iplying b a nd width vs. f r equenc y and code ? 0.8 ? 0.6 ? 0.4 ? 0.2 0 0.2 gain ( d b) 10k 1k 10 100 1 1 0 0 k 1 m 10m 1 00m frequency (hz) 04463-0-029 t a = 25c v dd = 5v v ref = 3.5v c comp = 1.8pf ad8038 amplifier AD5405 dac f i g u re 15. r e f e rence m u lt iply i n g b a nd widt hCa ll 1s l o ade d ?9 ?6 ?3 0 3 10k 100k 1m 10m 100m frequency (hz) t a = 25c v dd = 5v AD5405 gain ( d b) 04463-0-015 v ref = 2v, ad8038 c c 1.47pf v ref = 2v, ad8038 c c 1pf v ref = 0.15v, ad8038 c c 1pf v ref = 0.15v, ad8038 c c 1.47pf v ref = 3.51v, ad8038 c c 1.8pf f i g u re 16. r e f e rence m u lt iply i n g b a nd width vs. f r equenc y and comp ensat i on cap a cit o r
AD5405 rev. 0 | page 10 of 24 ?0.010 ?0.005 0.005 0.025 0.035 0.045 0.015 0 0.020 0.030 0.040 0.010 output voltage (v) 0 2 0 4 0 6 0 8 0 100 120 140 160 180 200 time (ns) 04463-0-039 t a = 25c v ref = 0v ad8038 amplifier c comp = 1.8pf 7ff to 800h 800 to 7ffh v dd = 5v v dd = 3v v dd = 3v v dd = 5v f i g u re 17. m i ds c a l e t r ans i t i on, v ref = 0 v output voltage (v) 0 2 0 4 0 6 0 8 0 100 120 140 160 180 200 time (ns) 04463-0-040 ?1.77 ?1.76 ?1.75 ?1.74 ?1.73 ?1.72 ?1.71 ?1.70 ?1.69 ?1.68 7ff to 800h 800 to 7ffh v dd = 5v v dd = 3v v dd = 3v v dd = 5v t a = 25c v ref = 3.5v ad8038 amplifier c comp = 1.8pf f i g u re 18. m i ds c a l e t r ans i t i on, v ref = 3 . 5 v ? 120 ? 100 ?80 ?60 0 20 1 100 1k 10k 100k 1m 10m frequency (hz) ?40 ?20 t a = 25 c v dd = 3v amp = ad8038 full scale zero scale psrr (d b) 04463-0-026 10 f i gure 19. p o wer s u p p ly rej e c t ion vs. f r equ e nc y ?90 ?85 ?80 ?75 ?70 ?65 ?60 thd + n (db) 100 1k 1 1 0 10k 100k 1m frequency (hz) 04463-0-041 t a = 25c v dd = 3v v ref = 3.5v p-p f i gure 20. thd and noise vs. f r equenc y 0 20 40 60 80 100 s f dr (db) 0 2 0 4 0 6 0 8 0 100 120 140 160 180 200 f out (khz) 04463-0-027 t a = 25c v ref = 3.5v ad8038 amplifier AD5405 mclk = 1mhz mclk = 200khz mclk = 0.5mhz f i g u re 21. wideb a n d sfdr v s . f ou t fre q u e n c y 0 10 20 30 40 50 60 70 80 90 s f dr (db) 0 100 200 300 400 500 600 700 800 900 1000 f out (khz) 04463-0-028 mclk = 5mhz mclk = 10mhz mclk = 25mhz t a = 25c v ref = 3.5v ad8038 amplifier AD5405 f i g u re 22. wideb a n d sfdr v s . f ou t fre q u e n c y
AD5405 rev. 0 | page 11 of 24 04463-0-018 ?9 0 ?7 0 ?5 0 ?3 0 ?1 0 s f dr (db) 0 frequency (mhz) ?8 0 ?6 0 ?4 0 ?2 0 0 t a = 25 c v dd = 5v amp = ad8038 AD5405 65k codes 2 4 6 8 10 12 f i g u re 23. wideb a n d sfdr , f ou t = 1 00 k h z, c l o c k = 2 5 m h z 04463-0-019 ?100 ?7 0 ?5 0 ?3 0 ?1 0 s f dr (db) 0 frequency (mhz) ?8 0 ?6 0 ?4 0 ?2 0 0 t a = 25 c v dd = 5v amp = ad8038 AD5405 65k codes 0.5 1.5 3.0 3.5 4.0 1.0 2.0 2.5 4.5 5.0 ?9 0 f i g u re 24. wideb a n d sfdr , f ou t = 5 0 0 k h z, c l o c k = 1 0 m h z 04463-0-020 ?9 0 ?7 0 ?5 0 ?3 0 ?1 0 s f dr (db) 0 frequency (mhz) ?8 0 ?6 0 ?4 0 ?2 0 0 0.5 1.5 3.0 3.5 4.0 1.0 2.0 2.5 4.5 5.0 t a = 25 c v dd = 5v amp = ad8038 AD5405 65k codes f i g u re 25. wideb a n d sfdr , f ou t = 5 0 k h z, c l o c k = 1 0 m h z 04463-0-021 frequency (mhz) t a = 25 c v dd = 3v amp = ad8038 AD5405 65k codes ?100 ?7 0 ?5 0 ?3 0 ?1 0 s f dr (db) 250 750 300 350 400 650 700 ?8 0 ?6 0 ?4 0 ?2 0 0 ?9 0 450 500 550 600 f i gure 26. na rro w - band spec tr al r e s p ons e , f ou t = 5 00 k h z, cl ock = 25 m h z 04463-0-022 ?120 ?6 0 ?2 0 s f dr (db) 50 150 frequency (mhz) 60 70 80 130 140 ?8 0 ?4 0 0 20 ?100 90 100 110 120 t a = 25 c v dd = 3v amp = ad8038 AD5405 65k codes f i gure 27. na rro w - band sf dr , f ou t = 1 00 k h z, c l ock = 2 5 mh z 04463-0-023 frequency (mhz) ?100 ?7 0 ?5 0 ?3 0 ?1 0 (db) 70 120 75 80 85 115 ?8 0 ?6 0 ?4 0 ?2 0 0 ?9 0 90 100 105 110 t a = 25 c v dd = 3v amp = ad8038 AD5405 65k codes 95 f i gure 28. na rro w - band imd , f ou t = 90 kh z, 10 0 k h z, c l oc k = 1 0 m h z
AD5405 rev. 0 | page 12 of 24 04463-0-024 ? 100 ?40 ?20 (db) ?50 ?30 ?10 ?90 ?60 ?70 ?80 0 400 frequency (khz) 50 300 350 100 150 200 250 0 t a = 25 c v dd = 5v amp = ad8038 AD5405 65k codes f i g u re 29. wideb a n d im d , f ou t = 90 kh z, 1 0 0 kh z , cl ock = 25 m h z 100 1k 10k 100k frequency (hz) t a = 25 c amp = ad8038 full scale loaded to dac zero scale loaded to dac 04463-0-025 0 50 100 150 200 250 300 outp ut nois e (nv / hz) midscale loaded to dac f i g u re 30. o u t p ut nois e spe c t r a l d e n s it y
AD5405 rev. 0 | page 13 of 24 terminology re l a ti ve a c c u r a c y rela t i v e acc u rac y o r en d p oin t n o nl inea r i ty is a m e as ur e o f th e maxim u m d e v i a t io n f r o m a st r a ig h t li ne p a ssing t h r o ug h t h e end p o i n t s o f t h e d a c t r a n sfer f u n c t i on. i t is me as ur e d a f t e r ad j u st ing fo r ze r o a n d f u l l s c a l e a nd is n o r m a l ly ex p r ess e d i n ls bs o r as a p e r c en t a g e o f f u l l -s cale r e adin g. d i f f erenti a l n o n l i n e a r i ty dif f er en t i al n o n l in e a r i ty is t h e dif f er en ce b e twe e n t h e m e as ur e d cha n ge and t h e ide a l 1 ls b chan ge b e twe e n an y tw o ad jace n t co des. a sp e c if i e d dif f er en t i a l no n l i n e a r i ty o f 1 ls b max o v er t h e o p era t i n g t e m p er a t ur e ra n g e en s u r e s m o n o t o nici ty . ga in er r o r ga in er r o r o r f u l l -s cale er r o r is a me as ur e o f t h e o u t p ut er r o r bet w een a n i d eal d a c a n d t h e act u al de v i ce o u t p u t . f o r th i s d a c, ide a l max i m u m o u tp u t is v ref ? 1 ls b . ga in er r o r o f th e d a cs is ad j u s t ab le t o zer o wi t h ext e r n al r e sis t a n ce. ou t p u t l e akage c u r r e n t o u t p u t le a k a g e c u r r en t is c u r r e n t t h a t f l o w s in t h e d a c ladder sw i t ch es w h en t h es e a r e t u r n e d o f f. f o r t h e i out 1 t e r m inal , i t can b e m e asur e d b y lo adin g a l l 0s to t h e d a c an d m e a s ur in g t h e i ou t 1 cu rr e n t . m i n i m u m cu rr e n t f l o w s i n th e i ou t 2 lin e w h en th e d a c is lo ade d wi t h al l 1s. ou t p u t c a pacita n c e ca pa c i t a n c e fr o m i ou t 1 o r i ou t 2 t o a g nd . o u tp u t c u r r e n t s e tt l i n g ti m e this is t h e am oun t o f tim e i t ta k e s f o r th e o u t p u t t o s e t t le t o a sp e c if ie d le ve l fo r a f u l l -s ca le i n p u t cha n ge . f o r t h is de vice , i t is s p ecif ie d wi t h a 100 ? r e sis t o r t o g r o u n d . dig i ta l t o ana l og glit ch lmp u ls e t h e a m ou n t of ch ar ge i n j e c t e d f r om t h e d i g i t a l i n put s to t h e a n alog o u t p u t w h en the in p u ts cha n g e s t a t e . this is typ i cal l y s p eci f i e d a s t h e a r ea o f th e gli t ch i n ei t h e r pa -s ecs o r n v -secs dep e n d in g up on w h et h e r t h e g l i t ch is m e asur e d as a c u r r en t or vol t age s i g n a l . dig i ta l f e e d thr o ug h w h en t h e de vic e is n o t s e le c t e d , hig h f r e q ue n c y log i c ac t i vi ty o n th e de v i ce s d i g i tal in p u ts i s ca pa ci ti v e l y co u p led th r o ugh t h e d e v i c e to show up a s noi s e on t h e i ou t p i ns and subs e q u e n t ly in t o t h e fol l o w i n g cir c ui t r y . this n o is e is dig i t a l fe e d t h r o ug h. m u l t iply in g f e e d thr o ug h e rro r this is t h e er r o r d u e t o c a p a ci t i v e fe e d t h r o ug h f r o m t h e d a c re f e re nc e i n put to t h e d a c i ou t 1 t e rm i n al , w h en all 0s a r e lo ade d t o the d a c. dig i ta l c r osstal k this is t h e g l i t ch im p u ls e t r a n sfer r e d t o t h e o u t p u t s o f o n e d a c in r e s p o n s e t o a full - s cal e c o d e c h a n g e (all 0 s t o all 1 s , a nd vice v e rs a) i n t h e in p u t r e g i s t er o f t h e o t h e r d a c. i t is exp r es s e d i n nv -s. ana l og c r ossta l k this is t h e g l i t ch im p u ls e t r a n sfer r e d t o t h e o u t p u t o f o n e d a c d u e to a ch a n ge i n t h e output of anot he r d a c . i t i s me a s u r e d by lo adin g on e o f t h e i n p u t r e g i st e r s wi t h a f u l l -s c a le co de chan ge (al l 0s t o al l 1s, a nd vice v e rs a), while k eep in g l d a c hig h . th en p u ls e ld a c lo w an d m o ni t o r t h e o u t p ut o f t h e d a c w h os e dig i t a l co de was n o t chan ge d . t h e a r e a o f t h e g l i t ch is ex p r ess e d in n v -s. c h an nel t o c h an nel i s ol a t i o n t h i s re f e r s to t h e prop or t i on of i n put s i g n a l f r om o n e d a c s r e fer e n c e i n p u t w h ich a p p e a r s a t t h e o u t p u t o f t h e o t h e r d a c, a nd is ex p r ess e d in dbs. t o t a l ha r m on i c d i s t or t i on ( t h d ) the d a c is dr i v en b y a n ac r e fer e n c e . the ra t i o o f t h e r m s s u m o f th e h a rm o n i c s o f th e d a c o u t p u t t o th e fun d a m en tal v a l u e i s t h e t h d . u s u a l l y on ly t h e l o we r - ord e r h a r m on i c s are i n clu d e d , s u ch as t h e s e cond t o t h e f i f t h. ( ) 1 2 5 2 4 2 3 2 2 log 20 v v v v v thd + + + = inte r m o d u l at i o n d i s t or t i on the d a c is dr i v en b y tw o com b i n e d si n e w a v e r e fer e n c es of f r e q u e nc i e s f a a n d f b . d i stor t i on pro d u c t s are pro d u c e d a t su m and dif f er en ce f r e q ue n c i e s o f mfa nfb w h er e m, n = 0, 1, 2, 3,... i n t e r m o d u l a t ion t e r m s a r e t h os e fo r w h ic h m o r n is not e q u a l to z e r o . t h e s e c o nd - o rd e r te r m s i n clu d e ( f a + f b ) a nd (fa ? fb) and the thir d-o r der t e r m s a r e (2fa + fb), (2fa ? fb), (f + 2fa + 2fb) a nd (fa ? 2fb). imd is def i n e d a s ( ) l fundamenta the of amplitude rms products distortion diff and sum the of sum rms imd log 20 = c o m p li ance v o l t age r a n g e the maxi m u m ra n g e o f (o u t p u t) t e r m inal v o l t a g e fo r w h ich t h e de vice p r o v i d es t h e sp e c if ie d ch a r ac t e r i st ics.
AD5405 rev. 0 | page 14 of 24 gene ral description dac section the AD5405 is a 12-b i t, d u al -cha nn e l , c u r r en t-o u t p u t d a c co n s ist i n g o f a st a n d a r d i n v e r t i n g r - 2 r lad d er co nf igura t io n. f i gur e 31 sh o w s a sim p lif i e d d i ag ra m fo r a sin g le cha n n e l o f t h e AD5405. th e f e ed back r e sis t o r r fb has a val u e o f 2r . th e val u e o f r is typ i cal l y 10 k? (minim u m 8 k? and maxim u m 12 k?). if i ou t 1a a nd i ou t 2a a r e k e p t a t t h e s a me p o t e n t ial , a con s t a n t c u r r en t f l o w s in e a c h ladder leg, r e ga r d les s o f dig i tal in p u t c o de . t h u s , t h e i n put re s i s t anc e pre s e n te d at v ref is a l wa y s co n s t a n t . v ref a i ou t 2 a dac data latches and drivers 2r s1 2r s2 2r s3 2r s12 2r r r r i out1a r fb a 2r 04463-0-005 f i gure 31. si mpl i fi e d ladde r co nfigur a t ion a c cess is p r o v id e d t o t h e v ref , r fb , i ou t 1, a n d i ou t 2 t e r m inals o f ea c h d a c , m a ki n g th e devi ce extr e m e l y v e r s a t i l e a n d all o w i n g i t t o b e co nf igure d i n s e v e ral dif f er en t o p era t in g m o des, s u ch as f o r u n ip o l ar output , bip o l a r output , or s i ng l e - s upply mo d e . circuit operation unipola r mo de u s in g a sin g le op a m p , t h is d a c can e a si ly b e co nf igur e d t o prov i d e 2 - q u a d r a n t m u lt iply i n g op e r a t i o n or a u n ip o l ar output v o l t a g e sw in g, as s h o w n in f i gur e 32. r fb 2r r1 2r AD5405 12-bit dac a r r1a r fb a v dd v ref a v out = 0v to ?v in a1 i out 2a i out 1a agnd c1 gnd agnd r2a r2_3a r3a r2 2r r3 2r agnd 04463- 0- 006 notes 1. similar configuration for dac b 2. c1 phase compensation (1pf ?2pf) may be required if a1 is a high speed amplifier. f i g u re 32. u n ipol ar o p er at io n w h en an o u t p ut a m plif ier is conn e c t e d in u n i p ola r m o de , t h e out p ut vol t ag e i s g i ve n b y ref n out v d v ? = 2 w h er e d is t h e f r ac t i o n al r e p r es en t a t i o n o f t h e dig i t a l w o r d loa d ed t o th e d a c , a n d n i s t h e r e so l u ti o n o f th e d a c . 4095 0 to d = w i t h a f i x e d 1 0 v re f e re nc e, t h e c i rc u i t s h ow n i n f i g u re 3 2 g i ve s a uni p ola r 0 v to ?10 v o u t p u t v o l t a g e s w i n g. w h en v in is a n ac sig n al, t h e cir c u i t p e r f o r m s 2-quadran t m u lt i p l i ca t i on. t a b l e 5 s h o w s th e r e la t i o n s h i p bet w een d i g i tal cod e a n d exp e c t e d ou t p u t v o l t a g e fo r uni p ola r o p era t io n. table 5. unip o l ar code table digital input analog output (v) 1111 1111 ?v ref (4095/4096) 1000 0000 ?v ref (2048/4096) = ?v ref /2 0000 0001 ?v ref (1/4096) 0000 0000 ?v ref (0/4096) = 0 bipolar operation i n so m e a p p l ica t io n s , i t ma y b e n e ces s a r y t o g e n e ra t e f u ll 4 - q u a d r a n t m u lt i p ly ing op er a t i o n or a bi p o l a r ou t p ut s w ing . this can be easi l y acco m p lish e d b y usin g a n o t her ext e r n al a m plif ier , as sh o w n in f i gur e 33. r fb 2r r1 2r AD5405 12-bit dac a r r1a r fb a v dd v ref a r2a r2_3a r3a a1 i out 2a i out 1a agnd c1 r2 2r r3 2r agnd gnd agnd a1 v in v out =? v in to +v in 04463- 0- 007 notes 1. similar configuration for dac b 2. c1 phase compensation (1pf ?2pf) may be required if a1 is a high speed amplifier. f i g u re 33. bipol a r o p er at ion ( 4 - q uad r ant m u lt ip li c a t i on ) w h en i n b i p o lar m o de , t h e o u t p u t v o l t a g e is g i v e n b y ref n ref out v d v v = ? 1 2 w h er e d is t h e f r ac t i o n al r e p r es en t a t i o n o f t h e dig i t a l w o r d lo aded t o the d a c, in t h e ra n g e o f 0 t o 4095, a nd n is t h e n u m b er o f b i t s. w h en v in is a n ac sig n al, t h e circ ui t p e r f o r m s 4-q u adra n t m u l t i p lic a tion. t a b l e 6 sh o w s t h e r e la t i o n s h i p b e tw e e n t h e dig i t a l co de and t h e e x pect ed o u t p u t v o l t a g e f o r b i pol a r o p e r a t i o n . table 6. bipola r code tabl e digital input analog output (v) 1111 1111 +v ref (2047/2048) 1000 0000 0 0000 0001 ?v ref (2047/2048) 0000 0000 ?v ref (2048/2048)
AD5405 rev. 0 | page 15 of 24 stability i n t h e i- t o -v conf igura t io n, t h e i ou t o f th e d a c a n d t h e in ver t ing no de o f t h e o p a m p m u st b e co n n e c te d a s clo s e as p o s s i b l e , and p r o p er pcb l a yo u t t e c h niq u es m u s t b e em p l o y ed . b e ca us e ev er y co de c h a n ge co r r es p o n d s t o a s t ep f u n c tio n , ga in p e akin g ma y o c c u r if t h e o p a m p has limi t e d g b p an d t h er e is exces s i v e p a rasi t i c ca p a c i t a n c e a t t h e i n v e r t in g n o de . this pa ra s i ti c ca pa c i ta n c e i n tr od u c e s a po l e i n t o th e o p e n l o o p re sp ons e w h i c h c a n c a u s e r i ng i n g or i n st a b i l it y i n t h e cl o s e d - l o o p ap p l i c at i o n s c i r c u i t . an o p t i o n a l com p e n s a t i on c a p a ci to r , c1, ca n b e adde d i n pa rall e l w i th r fb fo r st a b i l i t y , as sh own i n f i gur e 32 a nd f i gur e 33. t o o smal l a val u e o f c1 can p r o d uce r i n g in g a t t h e o u t p ut, w h i l e t o o la rg e a val u e c a n ad vers e l y a f fe c t t h e s e t t l i n g time . c1 sh o u ld be f o und em p i r i cal l y , b u t 1 pf to 2 pf is g e n e rall y ad e q ua t e f o r th e co m p en s a tio n . single-sup ply a pplic atio ns voltage swit ching mode of operation f i gur e 34 s h o w s t h es e d a cs o p era t in g in t h e vol t a g e s w i t chin g mo d e . t h e re f e re nc e vo lt ag e, v in , is a p plie d t o t h e i ou t 1 p i n, i ou t 2 is co nn e c te d t o a g nd , and t h e o u t p u t v o lt a g e is a v a i la b l e at t h e v ref t e r m ina l . i n t h is con f igura t io n, a p o s i t i v e r e fer e n c e volt age re su lt s i n a p o s i t i ve output volt ag e, ma k i ng s i ng l e - s u p p ly o p era t ion p o s s ib le . th e o u t p ut f r o m t h e d a c is v o l t a g e a t a con s t a n t im p e dan c e ( t h e d a c ladder r e sist a n c e ) . th us an o p a m p is n e cess a r y t o b u f f er t h e o u t p ut v o l t a g e. th e r e fer e n c e in p u t n o lo n g er s e es a co ns t a n t i n p u t i m p e dan c e , b u t on e t h a t va r i es wi t h co de. s o , t h e v o l t a g e in p u t sh o u ld b e dr i v en f r o m a lo w im p e dan c e s o ur ce . v out v dd gnd v in i out 2 i out 1 r fb v dd v ref r 2 r 1 04463-0-009 notes 1 . similar configuration for dac b 2 . c1 phase compensation (1pf? 2pf) may be required if a1 is a high speed amplifier. f i gure 34. sing le-s up ply v o ltag e s w itching m o de no t e t h a t v in is limi te d t o lo w vol t a g es b e c a us e t h e s w i t ch es i n t h e d a c ladder n o lo n g er ha ve t h e s a me s o ur ce -dra i n dr i v e vol t a g e. a s a r e su l t , t h eir on r e sist an ce dif f ers a nd deg r ades t h e in teg ral li n e a r i t y o f t h e d a c. a l s o , v in m u st no t go ne g a t i ve b y m o r e th a n 0 . 3 v o r a n i n t e rn al d i od e t u rn s o n , e x c eed i n g th e m a x ra ti n g s o f th e de v i ce . i n th is t y pe o f a p p l i c a t i o n , th e full ra n g e o f m u l t i p lyin g c a p a b i li ty o f t h e d a c is lo s t . posi tive o u tput voltage n o t e t h a t t h e ou t p ut v o l t a g e p o la r i ty is o p p o si t e t o t h e v ref p o la r i ty fo r dc r e fer e n c e v o l t a g e s . i n o r d er t o achie v e a p o si t i ve v o l t a g e o u t p ut, a n a p plie d nega t i v e r e fer e n c e t o t h e i n p u t o f t h e d a c is p r efer r e d o v er t h e o u t p ut i n v e rsio n t h r o u g h a n i n ve r t i n g am pl i f i e r b e c a u s e of t h e re s i stor s to l e r a nc e e r ror s . t o ge ne r a te a ne g a t i ve re f e re nc e, t h e re f e re nc e c a n b e l e vel s h i f te d b y a n o p a m p suc h tha t t h e v out an d g n d pi ns of t h e re f e re nc e b e c o m e t h e v i r t u a l g rou n d a n d ? 2 . 5 v re sp e c t i v e ly , a s s h ow n i n f i gur e 35. v out = 0v to +2.5v v dd = +5v gnd i out 2 i out 1 r fb v dd v ref c 1 gnd v in v out adr03 + 5v ?5v 1/2 ad8552 1/2 ad8552 12-bit dac ?2.5v 04463-0-010 notes 1 . similar configuration for dac b 2 . c1 phase compensation (1pf?2pf) may be required if a1 is a high speed amplifier. f i g u r e 3 5 . p o s i ti v e v o l t a g e ou t p u t w i th mi ni m u m c o m p o n e n t s adding g a in i n a p plic a t io n s w h er e t h e o u t p u t v o l t a g e is r e quir e d t o b e gr ea t e r th a n v in , ga in can b e ad de d w i t h an ad d i t i o n a l ex ter n a l a m p l if ier o r i t c a n als o b e ac hie v ed in a sing le sta g e . c o n s ider t h e ef fe c t o f t e m p er a t ur e co ef f i cien ts o f t h e t h i n f i lm r e sis t o r s o f t h e d a c. si m p ly placin g a resis t o r in s e r i es wi t h t h e r fb r e sis t o r ca us es misma t ch es i n t h e tem p e ra t u r e co ef f i cien ts r e s u l t in g i n la rger ga in t e m p er a t ur e co ef f i cien t er r o r s. i n s t e a d , t h e c i rc u i t of f i g u re 3 6 i s a re c o m m e n d e d me t h o d of i n c r e a s i ng t h e ga i n o f t h e cir c ui t. r 1 , r 2 , and r 3 sh o u ld al l ha v e simila r t e m p era t ur e co ef f i cien ts, b u t t h e y ne e d n o t ma tch t h e t e m p er - a t ur e co ef f i cien t s o f t h e d a c. this a p p r o a ch is r e co mme n d e d in cir c ui ts w h ere ga in s o f > 1 a r e r e q u ir e d . v out v dd gnd i out 2 i out 1 r fb v dd v ref c 1 12-bit dac r 3 r2 r2 v in r1 = r2r3 r2 + r3 gain = r2 + r3 r2 04463- 0- 011 notes 1 . similar configuration for dac b 2 . c1 phase compensation (1pf?2pf) may be required if a1 is a high speed amplifier. f i gure 36. inc r e a s i n g g a in of cu rrent o u tput d a c
AD5405 rev. 0 | page 16 of 24 used as a divider or programm able gain element u s e d as a di vi de r o r p r ogra mma b l e ga in e l e m en t, c u r r en t- s t e e r i n g d a cs ar e v e r y f l exi b l e a nd le n d t h ems e lv es t o man y dif f er en t a p plic a t io n s . i f t h is typ e o f d a c is conn e c t e d as t h e f eed ba ck e l em en t o f a n o p a m p , a n d r fb is us ed as th e in p u t re s i stor , a s show n i n fi g u re 3 7 , t h e n t h e output vo lt age i s i n v e r s e l y p r o p o r ti o n al t o th e digi tal in p u t f r a c tio n d . fo r d = 1 ? 2 n th e o u t p u t v o l t a g e i s ( ) n in in out v d v v ? ? ? = ? = 2 1 v out v dd gnd v in i out 2 i out 1 r fb v dd v ref note a dditional pins omitted for clarit y 04463-0-012 f i gure 37. cur r ent- stee ring d a c used as a d i v i d e r or p r og r a m m ab le g a i n e l e m ent a s d is r e d u ce d, t h e o u t p u t v o l t a g e i n cr e a s e s. f o r smal l val u es o f th e d i g i tal f r acti o n d , i t is im p o r t a n t t o en s u r e tha t t h e a m plif ier do es n o t s a t u ra te an d als o t h a t t h e r e q u ir e d acc u rac y is m e t. f o r exa m ple , a n 8 - b i t d a c dr i v en wi t h t h e b i na r y co de 0 10 (0001000 0), tha t is, 16 decimal , in t h e circ ui t o f f i gur e 37 s h o u ld ca us e t h e o u t p ut v o l t a g e t o b e 16 v in . h o w e v e r , i f t h e d a c has a li n e ar i t y sp e c if ic a t ion o f 0.5 ls b , t h e n d c a n, i n fac t , ha v e t h e weig h t an y w her e in t h e ra n g e 15. 5/256 t o 16.5/2 56 s o t h a t t h e p o s s ib le o u t p u t v o l t ag e is in t h e ra n g e 15.5 v in to 16.5 v in a n e r ror of 3 % e v e n t h ou g h t h e d a c it s e l f h a s a m a x i m u m e r ror of 0 . 2 % . d a c le aka g e c u r r en t is als o a p o t e n t ial er r o r s o ur ce in di vi der cir c ui ts. th e le a k a g e c u r r en t m u s t b e co u n t e rb alan ce d b y a n o p p o si t e c u r r en t s u p p lie d f r o m t h e o p am p t h r o ug h t h e d a c. b e ca us e o n ly a f r ac t i o n d o f t h e c u r r en t in t o t h e v ref te r m i n a l i s route d to t h e i ou t 1 t e r m inal, t h e o u t p ut v o l t a g e has t o cha n ge as fol l o w s: o u t p ut e r ror v o lt ag e d u e t o d a c l e ak ag e = ( l e ak ag e r ) / d w h er e r is t h e d a c r e sis t an ce a t t h e v ref te r m i n a l . f o r a d a c le aka g e c u r r en t o f 10 na, r = 10 k? a nd a ga i n (t ha t is, 1/d) o f 16, th e er r o r v o l t a g e is 1.6 mv . reference selection w h en s e lec t in g a r e f e r e n c e f o r us e wi t h t h e AD5405 s e r i es o f c u r r en t o u t p u t d a cs, p a y a t t e n t io n t o t h e r e fer e n c e o u t p u t v o l t a g e t e m p era t ur e co ef f i cien t s p e c if ic a t ion. this p a ra m e t e r n o t only a f fe c t s t h e f u l l -s cale er r o r , b u t ca n als o a f fe c t t h e lin e a r i t y (inl and d n l) p e r f o r ma nce . th e r e fe r e n c e tem p e r - a t ur e co ef f i cien t s h o u ld b e co n s i s t e n t wi t h t h e s y s t em acc u rac y sp e c if ic a t ion s . f o r exa m ple , a n 8-b i t syst e m r e quir e d t o h o ld i t s o v eral l s p e c if ica t ion t o wi t h i n 1 ls b o v er t h e t e m p era t ur e ra n g e 0c t o 50 c dic t a t es t h a t t h e maxi m u m s y s t em dr if t w i t h t e m p era t ur e sho u ld b e les s t h an 78 p p m/c. a 12-b i t sys t em wi t h t h e s a me tem p e r a t u r e rang e t o o v eral l s p e c if ica t ion wi t h i n 2 ls bs r e q u ir es a maxim u m dr i f t o f 10 p p m / c. b y ch o o sin g a p r e c isio n r e fer e n c e w i t h lo w o u t p u t t e m p era t ure co ef f i cien t, t h i s e r ror s o u r c e c a n b e m i n i m i z e d . t a bl e 7 l i s t s s o me re f e re nc e s a v a i la b l e f r o m analog d e vi ces t h a t a r e s u i t ab le fo r us e wi t h t h is ra n g e o f c u r r en t o u t p u t d a cs. amplifier selection the p r ima r y r e q u ir em e n t fo r t h e c u r r en t- s t e e r i n g m o de is a n a m plif ier wi t h lo w in p u t b i as c u r r en ts a nd lo w in p u t o f fs et volt age. t h e i n put of f s e t volt age of an op am p i s m u lt i p l i e d b y th e v a r i a b le g a in (d ue t o t h e co d e - d epen d e n t o u t p u t r e s i s t a n ce o f t h e d a c) o f t h e cir c ui t. a cha n g e i n t h is n o i s e ga in b e tw e e n tw o ad jacen t di g i t a l f r ac t i o n s pr o d uces a st ep cha n g e i n t h e o u t p ut v o l t a g e d u e t o t h e am plif ier s in p u t o f fs et v o l t a g e . thi s o u t p u t v o l t a g e cha n g e is s u p e r i m p os e d u p o n t h e desir e d c h ang e in o u t p u t b e tw e e n t h e t w o co de s a nd g i ves r i s e to a dif f er en t i a l lin e a r i t y er r o r , w h ich, if l a rg e en o u g h , co u l d ca us e t h e d a c t o b e n o n m on oto n ic. the i n pu t b i as c u r r en t o f an o p am p als o g e ner a t e s an o f fs e t a t t h e v o lt a g e out p u t as a r e s u l t o f t h e b i as c u r r e n t f l o w ing i n t h e fe e d bac k r e sist or r fb . m o st op am p s h a v e i n p u t b i as c u r r e n ts low e n o u g h t o p r e v e n t an y s i g n if i c an t er r o rs i n 1 2 - b i t a p pl i c a t i o ns. c o m m o n - m o d e re j e c t i o n of t h e op am p i s i m p o r t an t i n v o l t a g e- s w i t chi n g cir c ui ts, b e c a us e i t p r o d uces a co de - dep e n d e n t er r o r a t t h e v o l t a g e o u t p ut o f t h e ci r c ui t. m o s t o p a m ps ha ve ade q u a te co mm on- m o d e r e je c t ion fo r us e a t 12-b i t r e s o l u tion. p r o v ide d t h e d a c sw i t ch es a r e dr i v en f r o m t r ue wide b a nd , lo w im p e dan c e s o ur ces (v in and a g nd) t h e y s e t t le q u ick l y . c o n s eq ue n t l y , t h e s l ew ra t e a n d se t t li n g tim e o f a v o l t a g e- sw i t chin g d a c cir c ui t is det e r m i n e d la rg e l y b y t h e o u t p u t o p a m p . t o ob t a in mini m u m s e t t li n g t i m e i n t h is c o nf igura t io n, m i n i m i z e ca pa ci ta n c e a t th e v re f no de ( v ol t a ge o u t p ut no de i n t h is a p plic a t ion ) o f t h e d a c. this is do ne b y usin g lo w in p u t ca p a c i t a n c e b u f f er a m plif iers a nd ca r e f u l b o a r d desig n . m o st s i ng l e - s upply c i rc u i t s i n c l u d e g rou nd a s p a r t of t h e an a l o g sig n a l ra n g e , w h ich in t u r n r e q u ir es a n am plif ie r t h a t can han d l e ra il-t o-ra il signals. an alog devices o f f e r s a la r g e ra n g e o f sin g le- su p p ly a m plif ie rs, as list e d i n t a b l e 8.
AD5405 rev. 0 | page 17 of 24 table 7. suitable adi precision re fere nc es r e comme nded for use with AD5405 dacs reference output voltag e initial toleranc e tem perature d r ift 0.1 hz to 10 hz noise package adr01 10 v 0.1% 3 ppm/c 20 v p-p sc70, tsot, soi c adr02 5 v 0.1% 3 ppm/c 10 v p-p sc70, tsot, soi c adr03 2.5 v 0.2% 3 ppm/c 10 v p-p sc70, tsot, soi c adr425 5 v 0.04% 3 ppm/c 3.4 v p-p msop, soic table 8. precision adi op am ps su itable for use with ad54 05 dacs part no. max supply vo ltage v v os (max) v i b (max) na gbp mhz slew rate v/s op97 20 25 0.1 0.9 0.2 op1177 18 60 2 1.3 0.7 ad8551 +6 5 0.05 1.5 0.4 table 9. high s p ee d adi op amps suitable for use with AD5405 dacs part no. max supply vo ltage v v os (max) v i b (max) na bw @ a cl mh z slew rate v/s ad8065 12 1500 0.01 145 180 ad8021 12 1000 1000 200 100 ad8038 5 3000 0.75 350 425 parallel interf ace da t a is lo aded to th e AD5405 in the f o r m a t o f a 12-b i t p a ral l e l word. c o n t ro l l i ne s cs a nd r/ w a l l o w d a t a to b e w r it te n to or r e ad f r o m t h e d a c r e g i s t er . a w r i t e e v e n t t a k e s place w h en cs a nd r/ w a r e b r o u g h t lo w , da t a a v a i la b l e on t h e da t a l i n e s f i l l s t h e shif t r e g i st er , a n d t h e r i sin g e d g e o f cs la t c h e s th e da ta a n d t r a n sfers t h e l a tch e d da t a w o r d t o t h e d a c r e g i s t er . the d a c la t c h e s a r e n o t t r a n s p a r en t, t h us a wr i t e s e q u enc e m u s t co n s i s t o f a fa l l in g an d r i sin g e d ge o n cs t o en s u r e da t a is lo aded t o the d a c r e g i s t er and i t s a n alog e q u i valen t r e f l e c t e d o n t h e d a c o u t p ut. a r e ad e v en t t a k e s place w h en r / w is h e ld hig h and cs is b r o u g h t lo w . d a t a is lo ade d f r o m t h e d a c r e g i s t er b a ck t o t h e in p u t r e g i s t er and o u t on t o t h e da t a li ne w h er e i t can b e r e ad b a ck t o t h e con t r o l l er fo r v e r i f i ca t i o n o r di a g n o s t ic p u r p os es. the i n p u t and d a c r e g i s t ers of t h es e de vices ar e n o t t r an s- p a r e n t , s o a fa l l i n g an d r i sin g e d ge o f cs is r e q u ir ed t o lo ad ea c h d a ta -w o r d . microprocessor interfacing the AD5405 can b e in t e r f aced t o a va r i ety o f 16-b i t micr o- co n t r o l l ers o r ds p p r o c es s o rs. f i gur e 38 s h o w s t h e AD5405 d a c i n te r f ac e d to a ge ne r i c 1 6 - b i t mi c r o c on t r ol l e r / d s p pro c e s s o r . mi c ropro c e ss or i n te r f a c i n g to t h i s f a m i ly of d a c i s v i a a d a t a b u s t h a t us es a st andar d p r o t o c ol co m p a t ib le w i t h micr o c o n t r ol lers a nd dsp p r o c ess o rs. the address de co d e r s e l e c t s d a c a or d a c b and a l s o to l o ads p a r a l l el d a t a to t h e in p u t l a t c h o r t o r e ad da t a f r o m t h e d a c usin g a n a n d g a te . ad54xx* dac a/b cs wr db0 to db11 a0 to ax micro/dsp* wr db0 to db11 a address decoder data bus address bus a + 1 04462-0-055 *additional pins omitted for clarity f i g u re 38. a d 5 4 x x t o p a r a ll el inte r f ace pcb layou t an d p o w e r supply decou p lin g i n an y cir c ui t w h er e acc u rac y is im p o r t an t, ca r e f u l co n s ider - a t i o n of t h e p o we r supply an d g rou nd re tu r n l a y o ut h e lp s to en s u r e t h e ra te d p e r f o r ma n c e . th e p r i n t e d cir c ui t b o a r d o n whic h t h e ad5 405 is m o un t e d s h o u ld b e desig n e d s o tha t the a n a l o g a nd dig i t a l s e c t io n s a r e s e p a r a te d , an d c o nf in e d to cer t a i n a r e a s o f t h e b o a r d . i f t h e d a c is i n a syst em w h er e m u l t i p le de vice s r e q u ir e a n a g nd- t o - d g nd co nne c t io n, t h e co nne c t io n shou ld b e m a de a t o n e p o in t o n ly . the st a r g r o u n d p o in t sh o u ld b e es t a b l ish e d as cl os e as p o s s ib le to t h e de vice .
AD5405 rev. 0 | page 18 of 24 these dacs should have ample supply bypassing of 10 f in parallel with 0.1 f on the supply located as close to the pack- age as possible, ideally right up against the device. the 0.1 f capacitor should have low effective series resistance (esr) and effective series inductance (esi), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. low esr 1 f to 10 f tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough on the board. a microstrip technique is by far the best, but not always possible with a double-sided board. in this technique, the component side of the board is dedicated to the ground plane while signal traces are placed on the soldered side. it is good practice to employ compact, minimum lead length pcb layout design. leads to the input should be as short as possible to minimize ir drops and stray inductance. the pcb metal traces between v ref and r fb should also be matched to minimize gain error. to maximize high frequency performance, the i-to-v amplifier should be located as close to the device as possible. evaluation board for the dacs the evaluation board consists of a dac and a current-to- voltage amplifier, the ad8065. included on the evaluation board is a 10 v reference, the adr01. an external reference may also be applied via an smb input. the evaluation kit consists of a cd-rom with self-installing pc software to control the dac. the software simply allows the user to write a code to the device. power supplies for the evaluation board the board requires 12 v and 5 v supplies. the 12 v v dd and v ss are used to power the output amplifier, while the 5 v is used to power the dac (v dd1 ) and transceivers (v cc ). both supplies are decoupled to their respective ground plane with 10 f tantalum and 0.1 f ceramic capacitors.
AD5405 rev. 0 | page 19 of 24 04463- 0- 045 f i g u re 39. s c he mat i c of a d 5 4 05 ev a l uat i o n b o a r d
AD5405 rev. 0 | page 20 of 24 04463-0-046 f i g u re 40. co mpon ent - side a r t w ork 04463-0-047 f i gure 41. si lks c ree n c om pon e nt-si d e vie w ( t op laye r )
AD5405 rev. 0 | page 21 of 24 04463-0-048 f i gure 42. s o ld er -si d e a r t w o r k
AD5405 rev. 0 | page 22 of 24 overview of ad54xx devices table 10. part no. resolution no. dacs inl (lsb) interface package features ad5424 8 1 0.25 parallel ru-16, cp-20 10 mhz bw, 17 ns cs pulse width ad5426 8 1 0.25 serial rm-10 10 mhz bw, 50 mhz serial ad5428 8 2 0.25 parallel ru-20 10 mhz bw, 17 ns cs pulse width ad5429 8 2 0.25 serial ru-10 10 mhz bw, 50 mhz serial ad5450 8 1 0.25 serial rj-8 10 mhz bw, 50 mhz serial ad5432 10 1 0.5 serial rm-10 10 mhz bw, 50 mhz serial ad5433 10 1 0.5 parallel ru-20, cp-20 10 mhz bw, 17 ns cs pulse width ad5439 10 2 0.5 serial ru-16 10 mhz bw, 50 mhz serial ad5440 10 2 0.5 parallel ru-24 10 mhz bw, 17 ns cs pulse width ad5451 10 1 0.25 serial rj-8 10 mhz bw, 50 mhz serial ad5443 12 1 1 serial rm-10 10 mhz bw, 50 mhz serial ad5444 12 1 0.5 serial rm-8 10 mhz bw, 50 mhz serial ad5415 12 2 1 serial ru-24 10 mhz bw, 58 mhz serial ad5445 12 2 1 parallel ru-20, cp-20 10 mhz bw, 17 ns cs pulse width ad5447 12 2 1 parallel ru-24 10 mhz bw, 17 ns cs pulse width ad5449 12 2 1 serial ru-16 10 mhz bw, 50 mhz serial ad5452 12 1 0.5 serial rj-8, rm-8 10 mhz bw, 50 mhz serial ad5446 14 1 1 serial rm-8 10 mhz bw, 50 mhz serial ad5453 14 1 2 serial uj-8, rm-8 10 mhz bw, 50 mhz serial ad5553 14 1 1 serial rm-8 4 mhz bw, 50 mhz serial clock ad5556 14 1 1 parallel ru-28 4 mhz bw, 20 ns wr pulse width ad5555 14 2 1 serial rm-8 4 mhz bw, 50 mhz serial clock ad5557 14 2 1 parallel ru-38 4 mhz bw, 20 ns wr pulse width ad5543 16 1 2 serial rm-8 4 mhz bw, 50 mhz serial clock ad5546 16 1 2 parallel ru-28 4 mhz bw, 20 ns wr pulse width ad5545 16 2 2 serial ru-16 4 mhz bw, 50 mhz serial clock ad5547 16 2 2 parallel ru-38 4 mhz bw, 20 ns wr pulse width
AD5405 rev. 0 | page 23 of 24 outline dimensions 1 40 10 11 31 30 21 20 4.25 4.10 sq 3.95 top view 6.00 bsc sq pin 1 indicator 5.75 bcs sq 126 max 0.30 0.23 0.18 0.20 ref seating plane 1.00 0.85 0.80 0.05 max 0.02 nom coplanarity 0.08 0.80 max 0.65 typ 4.50 re f 0.50 0.40 0.30 0.50 bsc pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (b o t t o m view) compliant to jedec standards mo-220-vjjd-2 f i g u re 43. 4 0 l e ad lfcsp (c p - 4 0 ) d i mensions sh o w n in inc h es and ( m m) ordering guide model resolution inl (lsbs) temperature r a nge package descri ption package option AD5405ycp 12 1 ?40c to +125c lfcsp cp-40 AD5405ycpCre el 12 1 ?40c to +125c lfcsp cp-40 AD5405ycpCre el7 12 1 ?40c to +125c lfcsp cp-40 eval-AD5405 e b e v a l u a t i o n k i t
AD5405 rev. 0 | page 24 of 24 notes ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . d04463C0C 7/04(0)

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